Digital Design Verification Engineer
NVIDIA Corporation · Santa Clara, CA, United States ·
COMPENSATION
€•• – ••k
Listed on WeAreDevelopers
- 5+ years experience
- SystemVerilog & UVM
- SerDes IP focus
- Fully remote (EU)
- Senior level
We are seeking an experienced engineer to verify digital designs, golden models, and micro-architecture of SerDes IPs. You will utilize advanced methodologies like UVM to ensure design correctness within tight product shipment schedules.
What you'll do
- Verify digital design and micro-architecture of SerDes IPs using UVM
- Build reusable bus functional models, monitors, and scoreboards
- Define verification scope and develop necessary infrastructure
- Create test plans and execute verification under tight deadlines
- Collaborate with architects and silicon verification teams
What you'll need
- Bachelor's or Master's in Electrical/Computer Engineering or equivalent
- Minimum 5 years of validated verification experience
- Expertise in SystemVerilog and assertion-based verification
- Experience with random stimulus and functional coverage
- Proficiency with UVM/VMM methodologies and simulation tools
Nice to have
- Knowledge of bus protocols like PCI Express, USB, or SATA
- Experience verifying complex SerDes systems and mixed-signal designs
- Programming skills in Perl, Python, or C/C++
- Strong debugging and analytical capabilities
- Ability to model analog circuits
Stack
- SystemVerilog
- UVM
- Perl
- Python
- C/C++
- PCI Express
- USB
- SATA
- Formal Verification