Physical Design Engineer
Delos Data Inc · Remote · Palo Alto ·
COMPENSATION
€•• – ••k
Listed on the employer's job board (Ashby)
- Principal level role
- Hybrid US/Canada
- ASIC/SoC focus
- 10+ years exp
- Equity + 401(k)
Join an early-stage team backed by top-tier investors to solve scalability challenges in large-scale AI clusters. As a Principal Physical Design Engineer, you will drive critical blocks, establish methodologies, and provide technical leadership for high-performance chip designs.
What you'll do
- Own physical implementation of complex blocks from netlist to signoff
- Develop floorplans considering hierarchy, congestion, and timing
- Drive placement, CTS, routing, and timing closure
- Perform static timing analysis across multiple modes and corners
- Support power integrity analysis including IR drop and electromigration
- Partner with RTL and architecture teams to resolve implementation issues
- Develop and improve physical design flows and automation scripts
- Provide technical guidance and mentorship to other engineers
What you'll need
- 10+ years of ASIC or SoC physical design experience
- Multiple successful tapeouts required
- Expertise in floorplanning, placement, CTS, and routing
- Strong skills in static timing analysis and multi-corner closure
- Experience with Cadence or Synopsys implementation tools
- Proficiency in scripting with Tcl, Python, or Perl
- Ability to debug complex problems across RTL and physical domains
Nice to have
- Experience with advanced process nodes
- Background in large, high-frequency semiconductor designs
- Familiarity with multi-die or chiplet architectures
- Experience in early-stage semiconductor environments
- Knowledge of EDA tool evaluation and benchmarking
Stack
- Cadence
- Synopsys
- Tcl
- Python
- Perl
How you'll work
- Headquartered in Silicon Valley
- Hybrid remote and on-site work
- Locations in US and Canada
What you get
- Base salary $180k–$260k per year
- Meaningful equity package
- Health benefits included
- 401(k) plan available