Verification Engineer
Delos Data Inc · Remote · Palo Alto ·
COMPENSATION
€•• – ••k
Listed on the employer's job board (Ashby)
- Hybrid (US/Canada)
- SystemVerilog + UVM
- ASIC & FPGA focus
- 7+ years experience
- AI infrastructure
Join a Silicon Valley-backed startup developing foundational technology for large-scale AI data center clusters. The team addresses performance and scalability challenges in hardware infrastructure, led by experienced operators with successful exit histories.
As an RTL Verification Engineer, you will ensure the functionality and quality of complex digital designs. You will build robust verification environments, execute coverage-driven plans, and collaborate closely with RTL design engineers to deliver reliable silicon.
What you'll do
- Develop and maintain RTL verification environments using UVM or equivalent methodologies
- Create and execute coverage-driven verification plans aligned with design specs
- Develop directed and constrained-random test cases to validate functionality
- Debug complex verification issues and perform root-cause analysis with designers
- Implement functional and code coverage tracking to drive verification closure
- Develop reusable verification components and write SystemVerilog Assertions
- Automate regression testing and enhance infrastructure using Python scripting
- Participate in design reviews to provide input on testability and correctness
What you'll need
- Bachelor’s or Master’s degree in Electrical or Computer Engineering
- 7+ years of experience in digital design verification
- Strong hands-on experience with UVM-based verification methodologies
- Proficiency in SystemVerilog, UVM, and Python programming
- Experience with industry-standard EDA tools like VCS, Questa, or Xcelium
- Solid understanding of digital design fundamentals and protocols
- Experience verifying AXI, AXI-S, and APB bus interconnect protocols
- Knowledge of high-speed protocols such as PCIe, Ethernet, SPI, and I²C
Nice to have
- Experience with formal verification techniques and tools
- Background in verifying processor subsystems or SoC-level designs
Stack
- SystemVerilog
- UVM
- Python
- Synopsys VCS
- Siemens Mentor Questa
- Cadence Xcelium
- AXI
- PCIe
- Ethernet
How you'll work
- Headquartered in Silicon Valley
- Mix of remote and on-site locations
- Operates across the U.S. and Canada
What you get
- Meaningful equity package
- Standard benefits package
- 401(k) plan